Reset Recovery and Removal Time

Just like a clock, obliviously removing a reset can also cause a flip-flop to go into a metastable state. Like setup and hold time, there is a window before and after the active edge of clock during which the reset must not be removed. It is important to note that reset assertion is never a problem, it is the deassertion that we should be worried about. Let’s see what these reset checks are and their similarities with the setup and hold time.

Recovery Timing check

A recovery timing check ensures there is a minimum amount of time between the async signal becoming inactive and the next active clock edge. This check ensures that after the async signal becomes inactive, there is adequate time to recover so that the next active clock edge can be effective.

Like a setup check, this is a max path check, except that it is on an async signal.

Removal Timing check

This check ensures there is adequate time between an active clock edge and the release of an async control signal. The check ensures that the active clock edge has no effect on the output, because the async control signal remains active until removal time after the active clock edge. In other words, it is to check that the async control signal is released (aka become inactive) well after the active clock edge so that the clock can have no effect.

Like hold check, it is a min path check, except that it is on an async signal.

The picture below can help make these explanations clearer. Please have a look.

Reset recovery and removal timing diagram

That was a short article on reset recovery and removal time. Please comment below if you have any questions. I will see you in the next article!